View X5645_309293.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Replaces X25643/X25645
X5643/X5645
CPU Supervisor with 64Kb SPI EEPROM
FEATURES * Selectable Watchdog Timer * Low VCC Detection and Reset Assertion --Five standard reset threshold voltages --Re-program low VCC reset threshold voltage using special programming sequence --Reset signal valid to VCC=1V * Determine Watchdog or Low Voltage Reset with a Volatile Flag bit * Long Battery Life With Low Power Consumption --<50A max standby current, watchdog on --<1A max standby current, watchdog off --<400A max active current during read * 64K Bits of EEPROM * Built-In Inadvertent Write Protection --Power-up/power-down protection circuitry --Protect 0, 1/4, 1/2 or all of EEPROM array with Block LockTM protection --In circuit programmable ROM mode * 2MHz SPI Interface Modes (0,0 & 1,1) * Minimize EEPROM Programming Time --32 byte page write mode --Self-timed write cycle --5ms write cycle time (typical) * 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation * Available Packages --8-lead PDIP, 14-lead SOIC, 20-lead TSSOP BLOCK DIAGRAM
Watchdog Transition Detector WP SI SO SCK CS/WDI Data Register Command Decode & Control Logic VCC Threshold Reset logic Protect Logic RESET/RESET Status Register EEPROM Array 16K Bits 16K bits 32K bits Reset & Watchdog Timebase Watchdog Timer Reset
DESCRIPTION These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block LockTM Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time-out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the thresold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
X5643 = RESET X5645 = RESET
VCC VTRIP
Xicor, Inc. 2000 Patents Pending 9900-3002.5 3/31/00 EP
+ -
Power On and Low Voltage Reset Generation
Characteristics subject to change without notice.
1 of 22
X5643/X5645
PIN CONFIGURATION
14-Lead SOIC 8-Lead PDIP CS/WDI SO WP VSS 1 2 3 4 X5643/45 8 7 6 5 VCC RESET/RESET SCK SI NC CS/WDI CS/WDI SO WP VSS NC 20-Lead TSSOP NC CS/WDI SO NC NC NC WP NC NC NC 1 2 3 4 5 6 7 8 9 10 X5643/45 20 19 18 17 16 15 14 13 12 11 NC VCC RESET/RESET NC NC NC SCK SI NC NC 1 2 3 14 13 NC VCC VCC RESET/RESET SCK SI NC
12 4 X5643/45 11 5 6 7 10 9 8
PIN DESCRIPTION Pin PDIP
1
Pin SOIC
2&3
Pin TSSOP
2
Name
CS/WDI
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The absence of a HIGH to LOW transition within the watchdog timeout period results in RESET/RESET going active. Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the watchdog timer control and the memory write protect bits.
Characteristics subject to change without notice.
2 5
4 9
3 13
SO SI
6
10
14
SCK
3
5
7
WP
2 of 22
X5643/X5645
PIN DESCRIPTION (CONTINUED) Pin PDIP
4 8 7
Pin SOIC
6 12 & 13 11
Pin TSSOP
8 19 18
Name
VSS VCC RESET/ RESET Ground Supply Voltage
Function
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time-out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power up at about 1V and remains active for 200ms after the power supply stabilizes. No internal connections
1, 7, 8, 14
1, 4-6, 9-12, 15-17, 20
NC
PRINCIPLES OF OPERATION Power On Reset Application of power to the X5643/X5645 activates a power on reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/ RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5643/X5645 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The micorprocessor must toggle the CS/WDI pin periodically to prevent a RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time-out period. The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin LOW and setting the WPEN bit HIGH.
VCC Threshold Reset Procedure The X5643/X5645 has a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or for higher precision in the VTRIP value, the X5643/ X5645 threshold may be adjusted. Setting the VTRIP Voltage This procedure sets the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold to the Vcc pin and tie the CS/WDI pin and the WP pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to both SCK and SI and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete. Figure 1. Set VTRIP Voltage
CS VP SCK VP SI
Characteristics subject to change without notice.
3 of 22
X5643/X5645
Resetting the VTRIP Voltage This procedure sets the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, and the SCK pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete. Figure 3. VTRIP Programming Sequence Flow Chart
VTRIP Programming
Figure 2. Reset VTRIP Voltage
CS VCC
SCK
VP SI
Execute Reset VTRIP Sequence
Set VCC = VCC Applied = Desired VTRIP
New VCC Applied = Old VCC Applied + Error
Execute Set VTRIP Sequence
New VCC Applied = Old VCC Applied - Error
Apply 5V to VCC
Execute Reset VTRIP Sequence
Decrement VCC (VCC = VCC - 10mV)
NO RESET pin goes active?
YES Error Emax
Measured VTRIP Desired VTRIP Error < Emax
Error > Emax
Emax = Maximum Desired Error DONE
Characteristics subject to change without notice.
4 of 22
X5643/X5645
Figure 4. Sample VTRIP Reset Circuit
VP 4.7K 1 8 2 7 X5643/45 3 6 4 5 NC NC 4.7K RESET
NC VTRIP Adj. Program +
10K
10K
Reset VTRIP Test VTRIP Set VTRIP
SPI SERIAL MEMORY The memory portion of the device is a CMOS serial EEPROM array with Xicor's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Table 1. Instruction Set Instruction Name
WREN SFLB WRDI/RFLB RSDR WRSR READ WRITE
Write Enable Latch The device contains a write enable latch. This latch must be SET before a write operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7
WPEN
6
FLB
5
4
3
BL1
2
BL0
1
WEL
0
WIP
WD1 WD0
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress.
Instruction Format*
0000 0110 0000 0000 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 Set flag bit
Operation
Set the write enable latch (enable write operations) Reset the write enable latch/reset flag bit Read status register Write status register (watchdog, block lock, WPEN & flag bits) Read data from memory array beginning at selected address Write data to memory array beginning at selected address
Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Characteristics subject to change without notice.
5 of 22
X5643/X5645
Table 2. Block Protect Matrix WREN CMD WEL
0 1 1 1
Status Register WPEN
X 1 0 X
Device Pin WP#
X 0 X 1
Block Protected Block
Protected Protected Protected Protected
Block Unprotected Block
Protected Writable Writable Writable
Status Register WPEN, BL0, BL1 WD0, WD1
Protected Protected Writable Writable
The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When WEL=1, the latch is set HIGH and when WEL=0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. Status Register Bits BL1
0 0 1 1
The watchdog timer bits, WD0 and WD1, select the watchdog time-out period. These nonvolatile bits are programmed with the WRSR instruction. Status Register Bits WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time-Out (Typical)
1.4 seconds 600 milliseconds 200 milliseconds disabled
Array Addresses Protected X5643/X5645
None $1800-$1FFF $1000-$1FFF $0000-$1FFF
BL0
0 1 0 1
The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The flag bit is automatically reset upon power up. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time-out or power failure. The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide an in-circuit programmable ROM function (Table 2). WP is LOW and WPEN bit programmed HIGH disables all status register write operations. In Circuit Programmable ROM Mode This mechanism protects the block lock and watchdog bits from inadvertant corruption.
In the locked state (programmable ROM mode) the WP
pin is LOW and the nonvolatile bit WPEN is "1". This mode disables nonvolatile writes to the device's status register.
Characteristics subject to change without notice.
6 of 22
X5643/X5645
Figure 5. Read EEPROM Array Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
Instruction SI
16 Bit Address 15 14 13 3 2 1 0
Data Out High Impedance SO 7 MSB 6 5 4 3 2 1 0
Setting the WP pin LOW while WPEN is a "1" while an internal write cycle to the status register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the status register. When WP is HIGH, all functions, including nonvolatile writes to the status register operate normally. Setting the WPEN bit in the status register to "0" blocks the WP pin function, allowing writes to the status register when WP is HIGH or LOW. Setting the WPEN bit to "1" while the WP pin is LOW activates the programmable ROM mode, thus requiring a change in the WP pin prior to subsequent status register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the status register. Manufacturing can then load configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the "OTP mode" by setting the WPEN bit. Data changes now require a hardware change. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted
out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM array sequence (Figure 1). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 2). Write Sequence Prior to any attempt to write data into the device, the "Write Enable" Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be "0's". The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written.
Characteristics subject to change without notice.
7 of 22
X5643/X5645
For the page write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be "0" . While the write is in progress following a status register or EEPROM sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. OPERATIONAL NOTES The device powers-up in the following state: - The device is in the low power standby state. - A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. Figure 6. Read Status Register Sequence
CS
- SO pin is high impedance. - The write enable latch is reset. - The flag bit is reset. - Reset signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: - A WREN instruction must be issued to set the write enable latch. - CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
0 SCK
1
2
3
4
5
6
7
8
9
10
11 12 13 14
Instruction SI
Data Out SO High Impedance 7 MSB 6 5 4 3 2 1 0
Figure 7. Write Enable Latch Sequence
CS 0 SCK 1 2 3 4 5 6 7
SI
SO
High Impedance
Characteristics subject to change without notice.
8 of 22
X5643/X5645
Figure 8. Write Sequence
CS 0 SCK Instruction SI 16 Bit Address 15 14 13 32 Data Byte 1 321 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
1
0
7
6
5
4
0
CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 432 Data Byte 3 432 Data Byte N 4 32
SI
7
6
5
1
0
7
6
5
1
0
6
5
1
0
Figure 9. Status Register Write Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 7 6 5 4
Data Byte 3 2 1 0
SO
High Impedance
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
Characteristics subject to change without notice.
9 of 22
X5643/X5645
ABSOLUTE MAXIMUM RATINGS Temperature under bias ...................-65C to +135C Storage temperature ........................-65C to +150C Voltage on any pin with respect to vss ...... -1.0v to +7v D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300C RECOMMENDED OPERATING CONDITIONS Temp
Commercial Industrial
COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Device Option
-1.8 -2.7 or -2.7A Blank or -4.5A
Min.
0C -40C
Max.
70C +85C
Supply Voltage
1.8V-3.6V 2.7V to 5.5V 4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL
(1) (1)
Parameter
VCC write current (active) VCC read current (active) VCC standby current WDT=OFF VCC standby current WDT=ON VCC standby current WDT=ON Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Output HIGH voltage Reset output LOW voltage
Min.
Typ.
Max.
5 0.4 1 50 20
Units
mA mA A A A A A V V V V V V V V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC =3.6V VIN = VSS to VCC VOUT = VSS to VCC
0.1 0.1 -0.5 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4
VIH
VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLS
VCC > 3.3V, IOL = 2.1mA VCC 2V, IOL = 0.5mA
2V < VCC 3.3V, IOL = 1mA
VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4
VCC > 3.3V, IOH = -1.0mA VCC 2V, IOH = -0.25mA IOL = 1mA
2V < VCC 3.3V, IOH = -0.4mA
V
Characteristics subject to change without notice.
10 of 22
X5643/X5645
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol
COUT(2) CIN
(2)
Test
Output Capacitance (SO, RESET/RESET) Input Capacitance (SCK, SI, CS, WP)
Max.
8 6
Units
pF pF
Conditions
VOUT = 0V VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference on ly and are not tested. (2) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V 5V 4.6K
A.C. TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
2.06K Output 3.03K 100pF RESET/RESET
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing 1.8-3.6V Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI tFI
(3) (3)
2.7-5.5V Min.
0 500 250 250 200 250 50 50 100 100 100 100 500 10 10
Parameter
Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time
Min.
0 1000 500 500 400 400 50 50
Max.
1
Max.
2
Units
MHz ns ns ns ns ns ns ns ns ns ns ms
tCS tWC
(4)
500
Characteristics subject to change without notice.
11 of 22
X5643/X5645
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
SO
High Impedance
Serial Output Timing 1.8-3.6V Symbol
fSCK tDIS tV tHO tRO tFO
(3) (3)
2.7-5.5V Min.
0
Parameter
Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time
Min.
0
Max.
1 250 400
Max.
2 250 250
Units
MHz ns ns ns ns ns
0 100 100
0 100 100
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
Characteristics subject to change without notice.
12 of 22
X5643/X5645
Power-Up and Power-Down Timing
VTRIP VCC 0 Volts tR RESET (X5643) tPURST tPURST tF tRPD VTRIP
RESET (X5645)
RESET Output Timing Symbol
VTRIP
Parameter
Reset trip point voltage, X5643-4.5A, X5643-4.5A Reset trip point voltage, X5643, X5645 Reset trip point voltage, X5643-2.7A, X5645-2.7A Reset trip point voltage, X5643-2.7, X5645-2.7 Reset trip point voltage, X5643-1.8, X5645-1.8 VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up reset timeout VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC
Min.
4.5 4.25 2.85 2.55 1.7
Typ.
4.63 4.38 2.93 2.63 1.75 20
Max.
4.75 4.5 3.0 2.7 1.8
Units
V V V
VTH tPURST tRPD(5) tF
(5) (5)
mV 280 500 ms ns
s s
100 100 100 1
200
tR
VRVALID
V
Notes: (5) This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
tCST
RESET
tWDO tRST tWDO tRST
RESET
Characteristics subject to change without notice.
13 of 22
X5643/X5645
RESET/RESET Output Timing Symbol
tWDO
Parameter
Watchdog timeout period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS pulse width to reset the watchdog Reset timeout
Min.
100 450 1 400 100
Typ.
200 600 1.4 200
Max.
300 800 2 300
Units
ms ms sec ns ms
tCST tRST
VTRIP Set Conditions
tTHD VCC VTRIP tTSU tVPS tP tVPH tRP
CS
tVPS VP
tVPH
tVPO
SCK VP SI tVPO
VTRIP Reset Conditions
VCC* tRP tVPS tP tVP1
CS
tVPS
tVPH
tVPO
SCK
VCC
VP SI
tVPO
*VCC > Programmed VTRIP
Characteristics subject to change without notice.
14 of 22
X5643/X5645
Table 3. VTRIP Programming Specifications VCC=1.7-5.5V; Temperature = 0C to 70C Parameter
tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv
Description
SCK VTRIP program voltage setup time SCK VTRIP program voltage hold time VTRIP program pulse width VTRIP level setup time VTRIP level hold (stable) time VTRIP write cycle time VTRIP program cycle recovery period (between successive programming cycles) SCK VTRIP program voltage off time before next cycle Programming voltage VTRIP programed voltage range Initial VTRIP program voltage accuracy (VCC applied--VTRIP) (programmed at 25C) Subsequent VTRIP Program Voltage accuracy [(VCC applied--Vta1)--VTRIP) (programmed at 25C) VTRIP Program Voltage repeatability (successive program operations) (programmed at 25C) VTRIP program variation after programming (0-75C). (programmed at 25C)
Min.
1 1 1 10 10
Max. Units
s s s s ms 10 ms ms ms 18 5.0 +0.4 +25 +25 +25 V V V mV mV mV
10 0 15 1.7 -0.1 -25 -25 -25
VTRIP programming parameters are periodically sampled and are not 100% tested.
Characteristics subject to change without notice.
15 of 22
X5643/X5645
TYPICAL PERFORMANCE
VCC Supply Current vs. Temperature (ISB)
18 16 14 Reset (seconds) 12 Isb (uA) 10 8 6 4 2 0 -40 25 Temp (C) 90 Watchdog Timer Off (VCC = 3V, 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V)
tWDO vs. Voltage/Temperature (WD1,0=1,1)
1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1.7 2.4 3.1 3.8 Voltage 4.5 5.2 90C 25C -40C
VTRIP vs. Temperature (programmed at 25C)
5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature VTRIP=2.5V VTRIP=3.5V VTRIP=5V
tWDO vs. Voltage/Temperature (WD1,0=1,0)
0.8 0.75
Reset (seconds)
0.7 0.65 0.6 0.55 0.5 0.45 90C 25C
-40C
85
1.7
2.4
3.1 3.8 Voltage
4.5
5.2
tPURST vs. Temperature
205 200 195
tWDO vs. Voltage/Temperature (WD1,0 0=0,1)
205 200 195 Reset (seconds) 190 185 180 175 170 165 160 1.7 2.4 3.1 3.8 4.5 5.2 90C -40C 25C
190 Time (ms) 185 180 175 170 165
160 -40
25 Degrees C
90
Voltage
Characteristics subject to change without notice.
16 of 22
X5643/X5645
PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45 0.020 (0.50)
0.050"Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice.
17 of 22
X5643/X5645
PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice.
18 of 22
X5643/X5645
PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice.
19 of 22
X5643/X5645
PACKAGING INFORMATION 20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice.
20 of 22
X5643/X5645
Ordering Information VCC Range
4.5-5.5V
VTRIP Range
4.5.4.75
Package
8 pin PDIP 14L SOIC
Operating Temperature Range
0-70C 0-70C -40-85C 0-70C 0-70C -40-85C 0-70C 0-70C 0-70C
Part Number RESET (Active LOW)
X5643P-4.5A X5643S14-4.5A X5643S14I-4.5A X5643P X5643S14 X5643S14I X5643S14-2.7A X5643S14-2.7 X5643S14-1.8
Part Number RESET (Active HIGH)
X5645P-4.5A X5645S14-4.5A X5645S14I-4.5A X5645P X5645S14 X5645S14I X5645S14-2.7A X5645S14-2.7 X5645S14-1.8
4.5-5.5V
4.25.4.5
8 pin PDIP 14L SOIC
2.7-5.5V 2.7-5.5V 1.8-3.6V
2.85-3.0 2.55-2.7 1.7-1.8V
14L SOIC 14L SOIC 14L SOIC
Characteristics subject to change without notice.
21 of 22
X5643/X5645
Part Mark Information X5643/45 W X P = 8-Lead PDIP S14= 14 Lead SOIC Blank = 5V 10%, 0C to +70C, VTRIP=4.25-4.5 AL =5V10%, 0C to +70C, VTRIP = 4.5-4.75 I = 5V 10%, -40C to +85C, VTRIP=4.25-4.5 AM = 5V 10%, -40C to +85C, VTRIP=4.5-4.75 F = 2.7V to 5.5V, 0C to +70C, VTRIP=2.55-2.7 AN = 2.7V to 5.5V, 0C to +70C, VTRIP=2.85-3.0 G = 2.7V to 5.5V, -40C to +85C, VTRIP=2.55-2.7 AP = 2.7V to 5.5V, -40C to +85C, VTRIP=2.85-3.0 AG = 1.8V to 3.6V, 0C to +70C, VTRIP=1.7-1.8 AH = 1.8V to 3.6V, -40C to +85C, VTRIP=1.7-1.8
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. 2. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice.
22 of 22

▲Up To Search▲

Price & Availability of X5645

	To Download X5645 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .